01. June 2021

First full-readout with SADCs instead of QDCs First full readout with SADCs instead of QDCs

The CBELSA/TAPS experiment in Bonn has successfully completed its first readout using a full SADCs (sampling analogue-to-digital converters) setup instead of traditional QDCs (charge-to-digital converters). This upgrade allows higher data collection rates and improved feature extraction capabilities.

SADC Testboard
SADC Testboard © Johannes Müllers
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The CBELSA/TAPS collaboration at the University of Bonn has reached an important milestone by performing the first readout with a complete SADCs (sampling-analog-to-digital converters) setup, replacing the previously used QDCs (charge-to-digital converters).

The previously used QDCs integrated and digitized the energy information of an input signal using a capacitor and a traditional ADC. The new SADCs are implemented on FPGAs and digitize the input signal with a fixed sampling rate. By switching to SADCs, the experiment can handle higher data rates. In addition, the SADCs provide unique feature extraction capabilities. This leads to improved data quality through pile-up detection, event-based pedestal subtraction, and time information even for low-energy signals.

The first full readout with SADCs took place during the June 2021 data collection. While QDCs were still readout in parallel with SADCs at the beginning of the data collection, they were turned off after extensive data comparison to take advantage of the higher rate capabilities of the SADCs. The successful implementation of the full SADC configuration represents a significant upgrade of the experiment.